Computers typically include a plurality of electrical devices connected via one or more interconnects. The term “interconnect” generally refers to a mechanism linking together two or more devices. Such devices may include microprocessors, random access memory (“RAM”), read only memory (“ROM”), bridge logic, input/output (“I/O”) controllers, network interface controllers (“NICs”), etc. A bus generally comprises a collection of individual data, address and control signals which coordinate the efficient transmission of commands and responses between devices connected to the bus.
Interconnects may be categorized as “multi-drop” or “point-to-point” interconnects. A multi-drop interconnect permits three or more devices to be connected electrically on the same physical interconnect. In this configuration, one device may “master” a transaction while the other devices “listen” to activity on the interconnect. As such, the interconnect bandwidth is shared between the devices. A point-to-point interconnect permits only two devices to be electrically connected on the same physical interconnect. Various considerations exist when designing an interconnect structure and protocol. A multi-drop interconnect generally scales better when all the devices can be electrically tied together for example, by the electrical traces on the system board. If the number of devices to be interconnected is relatively large (for example, greater than 5), a bridge device may be used to create a new segment on which additional devices may be connected. However, while a multi-drop interconnect can be scaled to support a larger number of devices by using bridges, multi-drop interconnects are generally restrictive in the size of the topology as a result of additional considerations. Such considerations may include restrictions imposed by system board routing distance between the devices and a frequency limitation resulting from either the clock frequency becoming too high or signal quality degradation. A multi-drop interconnect also has the disadvantage of allowing one device to bring down all its neighboring devices that are electrically tied together on the same interconnect. By contrast, a point-to-point interconnect with only two devices connected on any of the interconnect links (or “segments”), may allow greater distances via electrical board traces or cabled interconnect between the devices and better reliability since all endpoints are generally electrically isolated from other devices via a hub or a switching device. As a result of using hubs or switching agents point-to-point interconnects typically include additional components (or the equivalent function included in one of the devices) to scale the system. A point-to-point interconnect that is linked via hubs exhibits similar characteristics to a multi-drop interconnect segment. In both cases, the bandwidth is shared between all the devices since only one device is permitted to master or initiate a transaction at a time. As a result, the mastering device could expose all devices to any failures in its interface protocol. A point-to-point interconnect connected via switches, however, not only isolates the devices electrically, like a hub, but also isolates packets (protocol), thereby allowing devices to send or receive packet information independently.
The computer and computer-related industries benefit from the promulgation of various standards governing the implementation and usage of various aspects of the computer. Various interconnect protocols are available and widely used to control the transfer of data. Examples of such interconnect standards include Peripheral Component Interconnect (“PCI”), PCI-X (a variation of PCI), Small Computer System Interface (“SCSI”), Industry Standard Architecture (“ISA”), etc. By using a standardized bus protocol, disparate device manufacturers can make computer-related components that, when assembled into the computer, will work together. The process of adopting and incorporating new standards into products is time consuming, expensive, and problematic from the perspective of backward compatibility to existing systems.
The PCI-X standard currently supports data rates of 266 megatransfers per second (“MT/s”) to 533 MT/s, but only in a point-to-point configuration. This is the case because PCI-X 266 and PCI-X 533 utilize a terminated signaling scheme to achieve the higher signaling rates. For embedded applications, which have typically used PCI-X in a multi-drop configuration, for cost effectively interconnecting 3–5 devices (not requiring hubs or switches to scale beyond 2-devices), the point-to-point restriction of PCI-X 266 and PCI-X 533 is viewed as a significant limitation. One solution to this problem might be to design a new bus protocol altogether. As explained above, this approach is time consuming and expensive. Thus, a solution which solves one or more of these problems is desirable.